preliminary mpeg clock generator with vcx o cy241v08-4 1 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07570 rev. ** revised september 8, 2003 features ? integrated phase-locked loop (pll) low-jitter, high-accuracy outputs vcxo with analog adjust 3.3v operation benefits highest-performance pll tailored for multimedia applica- tions meets critical timing requirements in complex system designs application compatibility for a wide variety of designs frequency table part number outputs input frequency range output frequencies vcxo control curve other features CY241V08-41 1 27-mhz pullable crystal input per cypress specification one copy of 27mhz one copy of 83.33mhz (non-pullable) linear pinout compatible with mk3741 27 xin xout osc vcxo vdd vss block diagram 8-pin soic CY241V08-41 1 2 3 4 xout xin vcxo xbuf/27 mhz vss ref 83.33 mhz 5 6 7 8 vdd pin configuration output divider pll 83.33mhz xbuf/27mhz 54 ref
preliminary cy241v08-4 1 document #: 38-07570 rev. ** page 2 of 6 pin descriptions for cy241v08 ?41 name pin number description xin 1 reference crystal input . vdd 2 voltage supply . vcxo 3 input analog control for vcxo . vss 4 ground . xbuf/27 mhz 5 27-mhz buffered crystal output . 83.33 mhz 6 83.33-mhz clock output . ref 7 54-mhz reference input . xout 8 reference crystal output .
preliminary cy241v08-4 1 document #: 38-07570 rev. ** page 3 of 6 absolute maximum conditions supply voltage (v dd ) ........................................?0.5 to +7.0v dc input voltage...................................... ?0.5v to v dd + 0.5 storage temperature (non-condensing).....?55 c to +125 c junction temperature ................................ ?40 c to +125 c data retention @ tj = 125 c................................> 10 years package power dissipation...................................... 350 mw esd (human body model) mil-std-883................. > 2000v (above which the useful life may be impaired. for user guide- lines, not tested.) pullable crystal specifications [1] parameter description comments min. typ. max. unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut ?27 ?mhz c lnom nominal load capacitance ? 14 ? pf r 1 equivalent series resistance (esr) fundamental mode ? ? 25 ? r 3 /r 1 ratio of third overtone mode esr to fundamental mode esr ratio used because typical r 1 values are much less than the maximum spec 3? ? ? dl crystal drive level no external series resistor assumed ? ? 150 w f 3sephi third overtone separation from 3*f nom high side 400 ? ? ppm f 3seplo third overtone separation from 3*f nom low side ? ? ?200 ppm c 0 crystal shunt capacitance ? ? 7 pf c 0 /c 1 ratio of shunt to motional capacitance 180 ? 250 ? c 1 crystal motional capacitance 14.4 18 21.6 ff recommended operating conditions parameter description min. typ. max. unit v dd operating voltage 3.135 3.3 3.465 v t a ambient temperature 0 ? 70 c c load max. load capacitance ? ? 15 pf t pu power-up time for all v dd pins to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms dc electrical specifications parameter name description min. typ. max. unit i oh output high current v oh = v dd ? 0.5v, v dd = 3.3v 12 24 ? ma i ol output low current v ol = 0.5v, v dd = 3.3v 12 24 ? ma c in input capacitance except xin, xout pins ? ? 7 pf v vcxo vcxo input range 0 ? v dd v f ? xo vcxo pullability range 150 ? ? ppm i vdd supply current ? ? 40 ma ac electrical specifications (v dd = 3.3v) [1] parameter [1] name description min. typ. max. unit dc output duty cycle duty cycle is defined in figure 1 , 50% of v dd 45 50 55 % er rising edge rate output clock edge rate, measured from 20% to 80% of v dd , c load = 15 pf. see figure 2 . 0.8 1.4 ? v/ns ef falling edge rate output clock edge rate, measured from 80% to 20% of v dd , c load = 15 pf. see figure 2 . 0.8 1.4 ? v/ns t 9 clock jitter 83.33 mhz peak-to-peak period jitter ? ? 500 ps t 9 clock jitter xbuf/27 mhz peak-to-peak period jitter ? ? 375 ps t 10 pll lock time ? ? 3 ms note: 1. not 100% tested.
preliminary cy241v08-4 1 document #: 38-07570 rev. ** page 4 of 6 voltage and timing definitions test and measurement set-up 0.1 f vdd outputs c load gnd dut ordering information ordering code package name package type operating range operating voltage features cy241v08sc-41 s8 8-pin soic commercial 3.3v linear vcxo control curve cy241v08sc-41t s8 8-pin soic ? tape and reel commercial 3.3v linear vcxo control curve clock output v dd 50% of v dd 0v t 1 t 2 figure 1. duty cycle definition clock output t 3 t 4 v dd 80% of v dd 20% of v dd 0v figure 2. er = (0.6 x v dd ) /t3, ef = (0.6 x v dd ) /t4
preliminary cy241v08-4 1 document #: 38-07570 rev. ** page 5 of 6 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimensions all product or company names mentioned in this document may be the trademarks of their respective holders. seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 8 lead (150 mil) soic - s08 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 8-lead (150-mil) soic s8 51-85066-*c
preliminary cy241v08-4 1 document #: 38-07570 rev. ** page 6 of 6 document history page document title: CY241V08-41 mpeg clock generator with vcxo document number: 38-07570 rev. ecn no. issue date orig. of change description of change ** 128866 09/09/03 ija new data sheet
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